We are committed to creating a dynamic working environment and motivating employees to better realize their self-worth

Job Title Job Type Work Place Operation

Job Description:

1、As part of the ASIC design team, engineer will mainly focus on following areas, but not limited to.

2、Deeply understand system level requirements and IP features, create sub-system design.

3、Deeply understand system level requirements and IP features, create sub-system design.

4、Assist with chip bring up and perform silicon functional/performance validation.

5、Assist with implementation team on netlist release, P&R suggestion and timing tuning.

Job Requirements:

1、 Degree in electrical engineering, computer engineering or related technical fields.

2、 Good knowledge of Verilog/SystemVerilog.

3、 Hand on experience on any of these tasks: Lint/CDC check, SDC/UPF generation, Synthesis, Formal.

4、 A high-level of self-motivation and a proactive approach to solving problems.

Job Requirements:

1、 Hands on experience on Subsystem level design.

2、 Familiar with Vendor’s PCIE controller and Phy, both function and test mode.

3、 Familiar with AMBA spec and SOC architecture.

4、 Familiar with frontend ASIC design methodology/flow.

5、 Experience of Low power design.

6、 Experience of follow IP is a strong plus: PCIE/UFS/USB/eMMC/GPU/ISP/MIPI/VPU/NPU/ DisplayPort/NoC/DDR/Ethernet/ AMBA AXI/AHB/APB/ GIC/SMMU/CoreSight.

Job Description:

As part of the ASIC design team, engineer will mainly focus on following areas, but not limited to:

1、Block, IP and SoC level DFT implementation including: RTL coding integration, Mbist insertion/simulation, Scan insertion & compression, Lbist insertion & simulaton, on chip clocking for at-speed test, boundary scan, analog/hard IP test.

2、Block level dft drc check & fix it in RTL/Netlist level.

3、Block level DFT constraint generation, synthesis, STA, ECO and formal check.

4、Test patterns/vectors generation and verification, Fault coverage data collection and improve.

Job Requirements:

1、Hand on experience of SoC DFT implementation, Scan Compression logic/MBIST logic/Boundary scan chain insertion, pattern bring up and diagnose.

2、 Expertise with Mentor/Synopsys DFT tools.

3、 Expertise with DFT advisor tools.

4、 Experience in MBIST/SCAN/ATPG Pattern simulation and debug on RTL & Netlist.

5、 A high-level of self-motivation and a proactive approach to solving problems.

Job Description:

As part of the ASIC design team, engineer will mainly focus on following areas, but not limited to:

1、Block, IP and SoC level DFT implementation including: RTL coding integration, Mbist insertion/simulation, Scan insertion & compression, Lbist insertion & simulaton, on chip clocking for at-speed test, boundary scan, analog/hard IP test.

2、Block level dft drc check & fix it in RTL/Netlist level.

3、Block level DFT constraint generation, synthesis, STA, ECO and formal check.

4、Test patterns/vectors generation and verification, Fault coverage data collection and improve.

Job Requirements:

1、Hand on experience of SoC DFT implementation, Scan Compression logic/MBIST logic/Boundary scan chain insertion, pattern bring up and diagnose.

2、 Expertise with Mentor/Synopsys DFT tools.

3、 Expertise with DFT advisor tools.

4、 Experience in MBIST/SCAN/ATPG Pattern simulation and debug on RTL & Netlist.

5、 A high-level of self-motivation and a proactive approach to solving problems.

Job Description:

As part of the ASIC design team, engineer will mainly focus on following areas, but not limited to:

1、Block, IP and SoC level DFT implementation including: RTL coding integration, Mbist insertion/simulation, Scan insertion & compression, Lbist insertion & simulaton, on chip clocking for at-speed test, boundary scan, analog/hard IP test.

2、Block level dft drc check & fix it in RTL/Netlist level.

3、Block level DFT constraint generation, synthesis, STA, ECO and formal check.

4、Test patterns/vectors generation and verification, Fault coverage data collection and improve.

Job Requirements:

1、Hand on experience of SoC DFT implementation, Scan Compression logic/MBIST logic/Boundary scan chain insertion, pattern bring up and diagnose.

2、 Expertise with Mentor/Synopsys DFT tools.

3、 Expertise with DFT advisor tools.

4、 Experience in MBIST/SCAN/ATPG Pattern simulation and debug on RTL & Netlist.

5、 A high-level of self-motivation and a proactive approach to solving problems.

Job Description:

1、SOC Design-For-Debug &Test methodology and micro architecture development.

2、ARM CoreSight micro architecture development and debug subsystem design and verification.

3、High performance and real-time cross-trigger engine design and verification for multi-core SOC.

4、Test-controller design and verification for PLL, MIPI, PCIE, USB3, DDR Debug and test.

5、Co-work with DFT team for SOC debug/test logic design and verification.

Job Requirements:

1、 Hand on experience of logic design.

2、 Be familiar with ARM CoreSight architecture.

3、 Be familiar with IEEE1149.1, IEEE 1149.6, IEEE 1500.

4、 Be familiar with Frontend design & implementation flow，Such as：Lint，CDC check，logic synthesis，formal；Be familiar with related EDA tools.

5、 Experience on analog IP testing is a plus.

6、 Familiar with unix/linux and scripts (tcl, perl, makefile etc.).

7、 Teamwork, A high-level of self-motivation and a proactive approach to solving problems.

Job Description:

1、SOC Design-For-Debug &Test methodology and micro architecture development.

2、ARM CoreSight micro architecture development and debug subsystem design and verification.

3、High performance and real-time cross-trigger engine design and verification for multi-core SOC.

4、Test-controller design and verification for PLL, MIPI, PCIE, USB3, DDR Debug and test.

5、Co-work with DFT team for SOC debug/test logic design and verification.

Job Requirements:

1、 Hand on experience of logic design.

2、 Be familiar with ARM CoreSight architecture.

3、 Be familiar with IEEE1149.1, IEEE 1149.6, IEEE 1500.

4、 Be familiar with Frontend design & implementation flow，Such as：Lint，CDC check，logic synthesis，formal；Be familiar with related EDA tools.

5、 Experience on analog IP testing is a plus.

6、 Familiar with unix/linux and scripts (tcl, perl, makefile etc.).

7、 Teamwork, A high-level of self-motivation and a proactive approach to solving problems.

Job Description:

1、SOC Design-For-Debug &Test methodology and micro architecture development.

2、ARM CoreSight micro architecture development and debug subsystem design and verification.

3、High performance and real-time cross-trigger engine design and verification for multi-core SOC.

4、Test-controller design and verification for PLL, MIPI, PCIE, USB3, DDR Debug and test.

5、Co-work with DFT team for SOC debug/test logic design and verification.

Job Requirements:

1、 Hand on experience of logic design.

2、 Be familiar with ARM CoreSight architecture.

3、 Be familiar with IEEE1149.1, IEEE 1149.6, IEEE 1500.

4、 Be familiar with Frontend design & implementation flow，Such as：Lint，CDC check，logic synthesis，formal；Be familiar with related EDA tools.

5、 Experience on analog IP testing is a plus.

6、 Familiar with unix/linux and scripts (tcl, perl, makefile etc.).

7、 Teamwork, A high-level of self-motivation and a proactive approach to solving problems.

Job Description:

As part of the ESL architecture team, engineer will mainly focus on following areas, but not limited to:

1、Architecture exploring for the complex SoC and high-speed subsystem include but not limited to memory, interconnection, ISP, GPU, CPU, and etc.

2、Bring up the virtual platform and analysis the performance and power simulation result.

3、Write the high quality SystemC/C++/TLM2 model for the memory, interconnection, and other high-speed subsystem.

4、Work out the highly configurable work load model for the various components in various scenarios.

5、Work out the SoC use case and performance goal in system level with help from product engineer.

6、Assist design engineer to work out the ASIC micro-architecture.

7、Co-work with verification engineer, design engineer, and software engineer to qualify and improve the quality of models.

Job Requirements:

1、 Degree in electrical engineering, computer engineering or related technical fields.

2、 Good knowledge of C++/SystemC modeling.

3、 Good knowledge on the Verilog and SystemVerilog.

4、 A high-level of self-motivation and a proactive approach to solving problems.

Solid knowledge in one of the following areas is a plus:

1、 Strong experience of high level modeling or software development with C++.

2、 experience of the ASIC design or verification.

3、 Familiar with AMBA AXI/AHB/APB spec.

4、 experience of GPU/VPU/DPU.

5、 experience of PCIE/USB/Ethernet/UFS/eMMC.

6、 Experience of low power design and power analysis.

7、 Experience of complex SoC modeling.

Job Description:

As part of the ESL architecture team, engineer will mainly focus on following areas, but not limited to:

1、Architecture exploring for the complex SoC and high-speed subsystem include but not limited to memory, interconnection, ISP, GPU, CPU, and etc.

2、Bring up the virtual platform and analysis the performance and power simulation result.

3、Write the high quality SystemC/C++/TLM2 model for the memory, interconnection, and other high-speed subsystem.

4、Work out the highly configurable work load model for the various components in various scenarios.

5、Work out the SoC use case and performance goal in system level with help from product engineer.

6、Assist design engineer to work out the ASIC micro-architecture.

7、Co-work with verification engineer, design engineer, and software engineer to qualify and improve the quality of models.

Job Requirements:

1、 Degree in electrical engineering, computer engineering or related technical fields.

2、 Good knowledge of C++/SystemC modeling.

3、 Good knowledge on the Verilog and SystemVerilog.

4、 A high-level of self-motivation and a proactive approach to solving problems.

Solid knowledge in one of the following areas is a plus:

1、 Strong experience of high level modeling or software development with C++.

2、 experience of the ASIC design or verification.

3、 Familiar with AMBA AXI/AHB/APB spec.

4、 experience of GPU/VPU/DPU.

5、 experience of PCIE/USB/Ethernet/UFS/eMMC.

6、 Experience of low power design and power analysis.

7、 Experience of complex SoC modeling.

Job Description:

As part of the ESL architecture team, engineer will mainly focus on following areas, but not limited to:

1、Architecture exploring for the complex SoC and high-speed subsystem include but not limited to memory, interconnection, ISP, GPU, CPU, and etc.

2、Bring up the virtual platform and analysis the performance and power simulation result.

3、Write the high quality SystemC/C++/TLM2 model for the memory, interconnection, and other high-speed subsystem.

4、Work out the highly configurable work load model for the various components in various scenarios.

5、Work out the SoC use case and performance goal in system level with help from product engineer.

6、Assist design engineer to work out the ASIC micro-architecture.

7、Co-work with verification engineer, design engineer, and software engineer to qualify and improve the quality of models.

Job Requirements:

1、 Degree in electrical engineering, computer engineering or related technical fields.

2、 Good knowledge of C++/SystemC modeling.

3、 Good knowledge on the Verilog and SystemVerilog.

4、 A high-level of self-motivation and a proactive approach to solving problems.

Solid knowledge in one of the following areas is a plus:

1、 Strong experience of high level modeling or software development with C++.

2、 experience of the ASIC design or verification.

3、 Familiar with AMBA AXI/AHB/APB spec.

4、 experience of GPU/VPU/DPU.

5、 experience of PCIE/USB/Ethernet/UFS/eMMC.

6、 Experience of low power design and power analysis.

7、 Experience of complex SoC modeling.

Job Description:

1、Responsible for Front-End chip implementation work from RTL2Netlist, including SOC/IP level Synthesis/STA/Formality check/Lint/CDC/Quality check.

2、Responsible for ASIC design methodology and flow development & optimization, interfacing with EDA vendors on technology.

3、Support Lint/CDC check, SDC/UPF writing.

4、Deliver constraints and closely co-work timing & power closure with P&R.

Job Requirements:

1、 Hand on experience of Synthesis/Formality/STA/LEC/SDC/UPF/Netlist quality check.

2、 Familiar with front-end EDA tools and flows (DCG, PT, Conformal, Formality, Spyglass, GCA).

3、 Familiar with unix/linux and scripts (tcl, perl, makefile etc.).

4、 Experience in highspeed interface IP, high performance Core is a plus.

5、 Experience in dft or physical design is a plus.

6、 A high-level of self-motivation and a proactive approach to solving problems.

Job Description:

1、Responsible for Front-End chip implementation work from RTL2Netlist, including SOC/IP level Synthesis/STA/Formality check/Lint/CDC/Quality check.

2、Responsible for ASIC design methodology and flow development & optimization, interfacing with EDA vendors on technology.

3、Support Lint/CDC check, SDC/UPF writing.

4、Deliver constraints and closely co-work timing & power closure with P&R.

Job Requirements:

1、 Hand on experience of Synthesis/Formality/STA/LEC/SDC/UPF/Netlist quality check.

2、 Familiar with front-end EDA tools and flows (DCG, PT, Conformal, Formality, Spyglass, GCA).

3、 Familiar with unix/linux and scripts (tcl, perl, makefile etc.).

4、 Experience in highspeed interface IP, high performance Core is a plus.

5、 Experience in dft or physical design is a plus.

6、 A high-level of self-motivation and a proactive approach to solving problems.

Job Description:

1、Responsible for Front-End chip implementation work from RTL2Netlist, including SOC/IP level Synthesis/STA/Formality check/Lint/CDC/Quality check.

2、Responsible for ASIC design methodology and flow development & optimization, interfacing with EDA vendors on technology.

3、Support Lint/CDC check, SDC/UPF writing.

4、Deliver constraints and closely co-work timing & power closure with P&R.

Job Requirements:

1、 Hand on experience of Synthesis/Formality/STA/LEC/SDC/UPF/Netlist quality check.

2、 Familiar with front-end EDA tools and flows (DCG, PT, Conformal, Formality, Spyglass, GCA).

3、 Familiar with unix/linux and scripts (tcl, perl, makefile etc.).

4、 Experience in highspeed interface IP, high performance Core is a plus.

5、 Experience in dft or physical design is a plus.

6、 A high-level of self-motivation and a proactive approach to solving problems.

Job Description:

Lead or co-lead the team to achieve verification target of state-of-the-art ARM based SoC, or one of its sub-system. Be responsible for verification quality and schedule.

1、Lead the verification process, decompose tasks for each team member.

2、Create verifcation plan and review with architecture/design team.

3、Create random constraint test bench based on the requirement.

4、Create random test cases and direct test cases to achieve coverage goals.

5、Work closely with architecture/design team to identify problems.

6、Low-power verification.

7、Performance verification.

8、Finish verification tasks on time.

  2. Job Requirements:

1、 Bachelor or above with more than 5 years’ work experience.

2、 Proficient with System Verilog & UVM.

3、 Expert in the use of Cadence/Synopsys verification tools.

4、 Verification experience on automotive chip is a great plus.

5、 CPU/GPU/ISP/DDR architecture knowledge is a great plus.

6、 high speed interface protocol knowledge is a great plus: PCIe/USB3.1/Ethernet, etc.

verification experience using Palladium/ZeBU is a great plus.

scripting languages (Python, Perl, Makefile, …) is an additional plus.

C and ARMv8.x assembly code programming skill is an additional plus.

Good communication skills.

Job Description:

Lead or co-lead the team to achieve verification target of state-of-the-art ARM based SoC, or one of its sub-system. Be responsible for verification quality and schedule.

1、Lead the verification process, decompose tasks for each team member.

2、Create verifcation plan and review with architecture/design team.

3、Create random constraint test bench based on the requirement.

4、Create random test cases and direct test cases to achieve coverage goals.

5、Work closely with architecture/design team to identify problems.

6、Low-power verification.

7、Performance verification.

8、Finish verification tasks on time.

  2. Job Requirements:

1、 Bachelor or above with more than 5 years’ work experience.

2、 Proficient with System Verilog & UVM.

3、 Expert in the use of Cadence/Synopsys verification tools.

4、 Verification experience on automotive chip is a great plus.

5、 CPU/GPU/ISP/DDR architecture knowledge is a great plus.

6、 high speed interface protocol knowledge is a great plus: PCIe/USB3.1/Ethernet, etc.

verification experience using Palladium/ZeBU is a great plus.

scripting languages (Python, Perl, Makefile, …) is an additional plus.

C and ARMv8.x assembly code programming skill is an additional plus.

Good communication skills.

Staff Style

Elite managers in the industry closely work together in SiEngine

Staff Style Work Environment